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1/26 december 2004 m36w0r5020t0 M36W0R5020B0 32 mbit (2mb x16, multiple bank, burst) flash memory and 4 mbit sram, 1.8v supply multi-chip package features summary multi-chip package ? 1 die of 32 mbit (2mb x 16) flash memory ? 1 die of 4 mbit (256kb x16) sram supply voltage ?v ddf = v ddq = v dds = 1.7 to 1.95v low power consumption electronic signature ? manufacturer code: 20h ? device code (top flash configuration): 8814h ? device code (bottom flash configuration): 8815h package ? compliant with lead-free soldering processes ? lead-free versions flash memory programming time ? 8s by word typical for fast factory program ? double/quadruple word program option ? enhanced factory program options memory blocks ? multiple bank memory array: 4 mbit banks ? parameter blocks (top or bottom location) synchronous / asynchronous read ? synchronous burst read mode: 66mhz ? asynchronous/ synchronous page read mode ? random access: 70ns dual operations ? program erase in one bank while read in others ? no delay between read and write operations figure 1. package block locking ? all blocks locked at power-up ? any combination of blocks can be locked ?wp f for block lock-down security ? 128-bit user programmable otp cells ? 64-bit unique device number common flash interface (cfi) 100,000 program/erase cycles per block sram access time: 70ns low v dds data retention: 1.0v power down features using two chip enable inputs fbga stacked tfbga88 (zaq)
m36w0r5020t0, M36W0R5020B0 2/26 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. tfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 address inputs (a0-a20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 data input/output (dq0-dq15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 flash chip enable (e f ).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 flash output enable (g f ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 flash write enable (w f ).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 flash write protect (wp f ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 flash reset (rp f ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 flash latch enable (l f ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 flash clock (k f ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 flash wait (wait f ).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 sram chip enable inputs (e1 s , e2 s ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 sram write enable (w s ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 sram output enable (g s ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 sram upper byte enable (ub s ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 sram lower byte enable (lb s ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v ddf supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v dds supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v ddq supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v ppf program supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v ss ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2. main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 flash memory component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 sram component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. sram block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 sram operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3/26 m36w0r5020t0, M36W0R5020B0 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 standby/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 output disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. ac measurement load circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 5. device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 6. flash memory dc characteristics - currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 7. flash memory dc characteristics - voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 8. sram dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 figure 8. sram read mode ac waveforms, address controlled with ub s = lb s = v il . . . . . . . 16 figure 9. sram read ac waveforms, g s controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 10.sram standby ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 9. sram read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 11.sram write ac waveforms, e1 s or e2 s controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 12.sram write ac waveforms, w s controlled, g s high during write . . . . . . . . . . . . . . . . 19 figure 13.sram write ac waveforms, w s controlled with g s low . . . . . . . . . . . . . . . . . . . . . . . 20 figure 14.sram write ac waveform, ub s and lb s controlled g s low . . . . . . . . . . . . . . . . . . . . 20 table 10. sram write ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 15.sram low v dds data retention ac waveforms, e1 s or ub s / lb s controlled . . . . . . 22 figure 16.sram low v dds data retention ac waveforms, e2 s controlled . . . . . . . . . . . . . . . . . 22 table 11. sram low v dds data retention characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 17. stacked tfbga88 8x10mm - 8x10 active ball array, 0.8mm pitch, package outline . . 23 table 12. stacked tfbga88 8x10mm - 8x10 active ball array, 0.8mm pitch, mechanical data . . 23 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 13. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 14. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
m36w0r5020t0, M36W0R5020B0 4/26 summary description the m36w0r5020t0 and M36W0R5020B0 com- bine two memory devices in a multi-chip package: a 32-mbit, multiple bank flash memory, the m58wr032ft/b and a 4-mbit sram. recommended operating conditions do not allow more than one memory to be active at the same time. the memory is offered in a stacked tfbga88 (8 x 10mm, 8x10 ball array, 0.8mm pitch) pack- age. in addition to the standard version, the package is also available in lead-free version, in compliance with jedec std j-std-020b, the st ecopack 7191395 specification, and the rohs (restriction of hazardous substances) directive. all packages are compliant with lead-free soldering processes. the memory supplied with all the bits erased (set to ?1?). figure 2. logic diagram table 1. signal names note: 1. a20-a18 are address inputs for the flash memory com- ponent only. ai08754b 21 a0-a20 dq0-dq15 m36w0r5020t m36w0r5020b g f 16 w f rp f wp f e1 s g s w s ub s lb s v ss v ddf v ppf v dds wait f l f k f v ddq e f e2 s a0-a20 (1) address inputs dq0-dq15 common data input/output v ddf flash memory power supply v ddq common flash and sram power supply for i/o buffers v ppf common flash optional supply voltage for fast program and erase v ss ground v dds sram power supply nc not connected internally du do not use as internally connected flash memory l f latch enable input e f chip enable input g f output enable input w f write enable input rp f reset input wp f write protect input k f burst clock wait f wait data in burst mode sram e1 s , e2 s chip enable input g s output enable input w s write enable input ub s upper byte enable input lb s lower byte enable input
5/26 m36w0r5020t0, M36W0R5020B0 figure 3. tfbga connections (top view through package) 8 7 6 5 4 3 2 1 c b nc k f a4 a11 d e f du du w f v ss a19 a18 nc a5 a12 v ss nc lb s a9 a3 a13 v ppf nc a17 a10 a20 a2 a15 l f wp f nc a7 a14 a8 a1 a16 rp f ub s a6 wait f dq13 a0 dq5 dq10 dq2 dq8 dq7 dq14 g s dq12 dq3 dq1 dq0 dq15 dq6 dq4 dq11 dq9 g f v ddq e f nc v dds v ss v ss v ss v ss v ss v ddf v ddq v ss du du du du du du a g h j k ai08755 l m v ddf nc w s e1 s nc nc nc nc nc e2 s nc nc v ddq
m36w0r5020t0, M36W0R5020B0 6/26 signal descriptions see figure 2., logic diagram and table 1., signal names , for a brief overview of the signals connect- ed to this device. address inputs (a0-a20). addresses a0-a17 are common inputs for the flash memory and sram components. the other lines (a18-a20) are inputs for the flash memory component only. the address inputs select the cells in the memory array to access during bus read operations. dur- ing bus write operations they control the com- mands sent to the command interface of the internal state machine. the flash memory is ac- cessed through the chip enable signal ( e f ) and through the write enable (w f ) signal, while the sram is accessed through two chip enable sig- nals (e1 s and e2 s ) and the write enable signal (w s ). data input/output (dq0-dq15). the data i/o output the data stored at the selected address dur- ing a bus read operation or input a command or the data to be programmed during a write bus op- eration. flash chip enable (e f ). the chip enable input activates the flash memory control logic, input buffers, decoders and sense amplifiers. when chip enable is low, v il , and reset is high, v ih , the device is in active mode. when chip enable is at v ih the flash memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. it is not allowed to set e f at v il, e1 s at v il and e2 s at v ih at the same time. flash output enable (g f ). the output enable pin controls data outputs during flash memory bus read operations. flash write enable ( w f ). the write enable in- put controls the bus write operation of the flash memory?s command interface. the data and ad- dress inputs are latched on the rising edge of chip enable or write enable whichever occurs first. flash write protect (wp f ). write protect is an input that gives an additional hardware protection for each block. when write protect is low, v il , lock-down is enabled and the protection status of the locked-down blocks cannot be changed. when write protect is at high, v ih , lock-down is disabled and the locked-down blocks can be locked or unlocked. (refer to lock status table in m58wr032ft/b datasheet). flash reset (rp f ). the reset input provides a hardware reset of the memory. when reset is at v il , the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the reset supply current i dd2 . refer to table 6., flash memory dc characteristics - cur- rents , for the value of i dd2 . after reset all blocks are in the locked state and the configuration reg- ister is reset. when reset is at v ih , the device is in normal operation. exiting reset mode the device enters asynchronous read mode, but a negative transition of chip enable or latch enable is re- quired to ensure valid data outputs. the reset pin can be interfaced with 3v logic with- out any additional circuitry. it can be tied to v rph (refer to table 7., flash memory dc characteris- tics - voltages ). flash latch enable (l f ). latch enable latches the address bits on its rising edge. the address latch is transparent when latch enable is low, v il , and it is inhibited when latch enable is high, v ih . latch enable can be kept low (also at board level) when the latch enable function is not required or supported. flash clock (k f ). the clock input synchronizes the flash memory to the microcontroller during synchronous read operations; the address is latched on a clock edge (rising or falling, accord- ing to the configuration settings) when latch en- able is at v il . clock is don't care during asynchronous read and in write operations. flash wait (wait f ). wait is a flash memory output signal used during synchronous read to in- dicate whether the data on the output bus are val- id. this output is high impedance when the flash memory chip enable is at v ih or reset is at v il . it can be configured to be active during the wait cy- cle or one clock cycle in advance. the wait f sig- nal is not gated by output enable. sram chip enable inputs (e1 s , e2 s ). the chip enable inputs activate the sram memory control logic, input buffers and decoders. e1 s at v ih with e2 s at v ih deselects the memory, reduc- ing the power consumption to the standby level, whereas e2 s at v il deselects the memory and re- duces the power consumption to the power-down level, regardless of the level of e1 s . e1 s and e2 s can also be used to control writing to the sram memory array, while w s remains at v il. it is not al- lowed to set e f at v il, e1 s at v il and e2 s at v ih at the same time. sram write enable (w s ). the write enable in- put controls writing to the sram memory array. w s is active low. sram output enable (g s ). the output enable gates the outputs through the data buffers during a read operation of the sram memory. g s is ac- tive low. sram upper byte enable (ub s ). the upper byte enable input enables the upper byte for sram (dq8-dq15). ub s is active low.
7/26 m36w0r5020t0, M36W0R5020B0 sram lower byte enable (lb s ). the lower byte enable input enables the lower byte for sram (dq0-dq7). lb s is active low. v ddf supply voltage. v ddf provides the power supply to the internal core of the flash memory component. it is the main power supply for all flash memory operations (read, program and erase). v dds supply voltage. v dds provides the power supply to the internal core of the sram device. it is the main power supply for all sram operations. v ddq supply voltage. v ddq provides the power supply for the flash memory and sram i/o pins. this allows all outputs to be powered indepen- dently of the flash memory and sram core power supplies: v ddf and v dds , respectively. v ppf program supply voltage. v ppf is a flash memory power supply pin. the supply voltage v ddf and the program supply voltage v pp can be applied in any order. the pin can also be used as a control input for the flash memory. the two functions are selected by the voltage range applied to the pin. if v ppf is kept in a low voltage range (0v to v ddq ) v ppf is seen as a con- trol input. in this case a voltage lower than v pplk gives an absolute protection against program or erase, while v ppf > v pp1 enables these functions (see tables 6 and 7 , dc characteristics for the rel- evant values). v ppf is only sampled at the begin- ning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. if v ppf is in the range of v pph it acts as a power supply pin. in this condition v ppf must be stable until the program/erase algorithm is completed. v ss ground. v ss is the common ground refer- ence for all voltage measurements in the flash memory (core and i/o buffers) and sram compo- nents. note: each flash memory device in a system should have its supply voltage (v ddf ) and the program supply voltage v ppf decoupled with a 0.1f ceramic capacitor close to the pin (high frequency, inherently low inductance capaci- tors should be as close as possible to the package). see figure 7., ac measurement load circuit . the pcb track widths should be sufficient to carry the required v ppf program and erase currents.
m36w0r5020t0, M36W0R5020B0 8/26 functional description the flash memory and sram components have separate power supplies but share the same grounds. they are distinguished by three chip en- able inputs: e f for the flash memory and e1 s and e2 s for the sram. recommended operating conditions do not allow more than one device to be active at a time. the most common example is simultaneous read oper- ations on the flash memory and sram compo- nents which would result in a data bus contention. therefore it is recommended to put the other de- vices in the high impedance state when reading the selected device. figure 4. functional block diagram ai08756b e1 s e2 s g s w s dq0-dq15 v ddf a0-a17 a18-a20 4mbit sram g f ub s lb s wait f 32 mbit flash memory v dds e f k f w f l f rp f wp f v ppf v ddq v ss
9/26 m36w0r5020t0, M36W0R5020B0 table 2. main operating modes note: 1. x = don't care. 2. l f can be tied to v ih if the valid address has been previously latched. 3. depends on g f . 4. wait signal polarity is configured using the set configurati on register command. refer to m58wr032ft/b datasheet for details. operation e f g f w f l f rp f wait f (4) e1 s e2 s g s w s ub s lb s dq15-dq0 flash read v il v il v ih v il (2) v ih sram must be disabled flash data out flash write v il v ih v il v il (2) v ih flash data in flash address latch v il x v ih v il v ih flash data out or hi-z (3) flash output disable v il v ih v ih x v ih any sram mode is allowed flash hi-z flash standby v ih xx x v ih hi-z flash hi-z flash reset x x x x v il hi-z flash hi-z sram read flash memory must be disabled v il v ih v il v ih v il v il sram data out sram write v il v ih x v il v il v il sram data in output disable any flash mode is allowed. v il v ih v ih v ih v il v il sram hi-z sram standby v ih xxxxx sram hi-z x v il xxxx sram hi-z
m36w0r5020t0, M36W0R5020B0 10/26 flash memory component the m36w0r5020t0 and M36W0R5020B0 con- tain a 32 mbit flash memory. for detailed informa- tion on how to use it, see the m58wr032ft/b datasheet which is available from your local stmi- croelectronics distributor. sram component the m36w0r5020t0 and M36W0R5020B0 con- tain a 4 mbit sram. see figure 5., sram block diagram in conjunction with the sram opera- tions section, table 2., main operating modes and the sram ac waveforms and characteristics for details. figure 5. sram block diagram data in drivers 256k x16 ram array 2048 x 2048 column decoder row decoder a0-a10 w s ub s lb s sense amps a11-a17 power-down circuit dq0-dq7 dq8-dq15 g s ub s lb s ai08706b e1 s e2 s e1 s e2 s
11/26 m36w0r5020t0, M36W0R5020B0 sram operations there are five standard operations that control the device. these are read, write, standby/power- down, data retention and output disable. read. read operations are used to output the contents of the sram array. the device is in byte read mode whenever write enable, w s , is at v ih , output enable, g s , is at v il , chip enable, e1 s , is at v il , chip enable, e2 s , is at v ih , and ub s or lb s is at v il . the device is in word read mode whenever write enable, w s , is at v ih , output enable, g s , is at v il , byte enable inputs ub s and lb s are both at v il and the two chip enable inputs, e1 s , and e2 s are don?t care. the read and standby ac waveforms are shown in figures 9 and 10 , respectively and the parame- ters are given in table 9. , sram read ac char- acteristics . write. write operations are used to write data to the sram. the device is in write mode whenever w s , e1 s and ub s and/or lb s are at v il , and e2 s is at v ih . all these signals must be asserted to ini- tiate a write cycle. the data is latched on the fall- ing edge of e1 s , the rising edge of e2 s , the falling edge of w s , or the falling edge of ub s and/or lb s , whichever occurs last. the write cycle will termi- nate on the rising edge of e1 s , the rising edge of w s , the rising edge of ub s and/or lb s , or the fall- ing edge of e2 s , whichever occurs first. the tim- ings are referenced to the signal that terminates the write cycle. the outputs are disabled during write cycles (whenever e1 s , at v il , e2 s at v ih , and w s at v il ). the write ac waveforms are shown in figures 11 , 12 , 13 and 14 , while table 10. gives the write ac characteristics. standby/power-down. the device automatically enters the standby/power-down mode when dq0-dq15 are not toggling, reducing the power consumption to the standby level, i sb . the device is also in standby/power-down mode whenever e1 s is at v ih , e2 s is at v il or both ub s and lb s are at v ih . the outputs then become high impedance. the standby ac waveforms are shown in figure 10. see table 9. , sram read ac characteristics , for timings. data retention. the data retention mode is en- tered t cdr after de-asserting e1 s , e2 s or ub s and lb s . the data retention performance as v dd goes down to v dr is described in table 11. , figures 15 and 16 , sram low v dds data retention ac waveforms, e1 s or ub s / lb s controlled and sram low v dds data retention ac waveforms, e2 s controlled , respectively. output disable. the device is in the output dis- able mode whenever g s , is at v ih . in this mode, dq0-dq15 are high impedance.
m36w0r5020t0, M36W0R5020B0 12/26 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 3. absolute maximum ratings note: 1. compliant with the jedec std j-std-020b (for small body, sn-pb or pb assembly), the st ecopack ? 7191395 specification, and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu. symbol parameter value unit min max t a ambient operating temperature ?40 85 c t bias temperature under bias ?40 125 c t stg storage temperature ?65 155 c t lead lead temperature during soldering (1) c v io input or output voltage ?0.5 v ddq +0.6 v v ddf flash memory core supply voltage ?0.2 2.45 v v ddq input/output supply voltage ?0.2 2.45 v v dds sram supply voltage ?0.2 2.4 v v ppf flash memory program voltage ?0.2 14 v i o output short circuit current 100 ma t vppfh time for v ppf at v ppfh 100 hours
13/26 m36w0r5020t0, M36W0R5020B0 dc and ac parameters this section summarizes the operating measure- ment conditions, and the dc and ac characteris- tics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 4., operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. table 4. operating and ac measurement conditions figure 6. ac measurement i/o waveform figure 7. ac measurement load circuit table 5. device capacitance note: sampled only, not 100% tested. parameter flash memory sram unit min max min max v ddf supply voltage 1.7 1.95 ? ? v v dds supply voltage ??1.71.95v v ddq supply voltage 1.7 1.95 ? ? v v ppf supply voltage (factory environment) 11.4 12.6 ? ? v v ppf supply voltage (application environment) ?0.4 v ddq +0.4 ??v ambient operating temperature ?40 85 ?40 85 c load capacitance (c l ) 30 30 pf output circuit resistors (r 1 , r 2 ) 16.7 16.7 k ? input rise and fall times 5 1 ns input pulse voltages 0 to v ddq 0 to v dds v input and output timing ref. voltages v ddq /2 v dds /2 v ai06161 v ddq 0v v ddq /2 ai08364b v ddq c l c l includes jig capacitance r 1 device under test 0.1f v ddq r 2 0.1f v ddf symbol parameter test condition min max unit c in input capacitance v in = 0v 12 pf c out output capacitance v out = 0v 15 pf
m36w0r5020t0, M36W0R5020B0 14/26 table 6. flash memory dc characteristics - currents note: 1. sampled only, not 100% tested. 2. v ddf dual operation current is the sum of read and program or erase currents. symbol parameter test condition min typ max unit i li input leakage current 0v v in v ddq 1 a i lo output leakage current 0v v out v ddq 1 a i dd1 supply current asynchronous read (f=6mhz) e f = v il , g f = v ih 36ma supply current synchronous read (f=54mhz) 4 word 7 16 ma 8 word 10 18 ma 16 word 12 22 ma continuous 13 25 ma supply current synchronous read (f=66mhz) 4 word 8 17 ma 8 word 11 20 ma 16 word 14 25 ma continuous 16 30 ma i dd2 supply current (reset) rp f = v ss 0.2v 10 50 a i dd3 supply current (standby) e f = v ddf 0.2v 10 50 a i dd4 supply current (automatic standby) e f = v il , g f = v ih 10 50 a i dd5 (1) supply current (program) v ppf = v pph 815ma v ppf = v ddf 10 20 ma supply current (erase) v ppf = v pph 815ma v ppf = v ddf 10 20 ma i dd6 (1,2) supply current (dual operations) program/erase in one bank, asynchronous read in another bank 13 26 ma program/erase in one bank, synchronous read in another bank 23 45 ma i dd7 (1) supply current program/ erase suspended (standby) e f = v ddf 0.2v 10 50 a i pp1 (1) v ppf supply current (program) v ppf = v pph 25ma v ppf = v ddf 0.2 5 a v ppf supply current (erase) v ppf = v pph 25ma v ppf = v ddf 0.2 5 a i pp2 v ppf supply current (read) v ppf v ddf 0.2 5 a i pp3 (1) v ppf supply current (standby) v ppf v ddf 0.2 5 a
15/26 m36w0r5020t0, M36W0R5020B0 table 7. flash memory dc characteristics - voltages table 8. sram dc characteristics symbol parameter test condition min typ max unit v il input low voltage ?0.5 0.4 v v ih input high voltage v ddq ?0.4 v ddq + 0.4 v v ol output low voltage i ol = 100a 0.1 v v oh output high voltage i oh = ?100a v ddq ?0.1 v v pp1 v ppf program voltage-logic program, erase 1.1 1.8 3.3 v v pph v ppf program voltage factory program, erase 11.4 12 12.6 v v pplk program or erase lockout 0.4 v v lko v ddf lock voltage 1v v rph rp f pin extended high voltage 3.3 v symbol parameter test condition min max unit i li input leakage current 0v v in v dd 1 a i lo output leakage current 0v v out v dds , output disabled 1 a i dds v dd standby current e1 s v dds ? 0.2v or e2 s 0.2v v in v dds ? 0.2v or v in 0.2v f = f max (address and data inputs only) f = 0 (g s , w s , ub s and lb s ) 10 a e1 s v dds ? 0.2v or e2 s 0.2v v in v dds ? 0.2v or v in 0.2v f = 0, v dd (max) 10 a i dd supply current f = f max = 1/t avav , cmos levels v dds = v dds (max) 6ma i out = 0 ma, f = 1mhz, cmos levels 3ma v il input low voltage ?0.2 0.4 v v ih input high voltage 1.4 v dds +0.2 v v ol output low voltage i ol = 0.1ma, v dsd = 1.65v 0.2 v v oh output high voltage i oh = ? 0.1ma, v dds = 1.65v 1.4 v
m36w0r5020t0, M36W0R5020B0 16/26 figure 8. sram read mode ac waveforms, address controlled with ub s = lb s = v il note: e1 s = low, e2 s = high, g s = low, w s = high. figure 9. sram read ac waveforms, g s controlled note: 1. ub s , lb s means both ub s and lb s . 2. write enable (w s ) = high. address valid prior to or at the same time as e1 s and ub s , lb s go low and e2 s goes high. figure 10. sram standby ac waveforms ai09881 tavav tavqv tavqx a0-a17 dq0-dq15 valid data valid data valid ai09882 te1le1h te2he2l te1lqv te2hqv te1hqz tglqv tglqx tghqz data valid a0-a17 e1 s g s dq0-dq15 te1lqx te2hqx valid te2lqz e2 s lb s , ub s tblqx tbhqz ai08192 tpd e2 s i dd tpu 50% e1 s i dds
17/26 m36w0r5020t0, M36W0R5020B0 table 9. sram read ac characteristics note: 1. sampled only. not 100% tested. 2. whatever the temperature and voltage, t e1hdz and t e2ldz are less than t e1ldx and t e2hdx ; t bhdz is less than t bldx and, t ghdz is less than t ghdx . symbol alt parameter m36w0r5020t0, M36W0R5020B0 unit min max t avav t e1le1h t e2he2l t rc read cycle time 70 ns t avqv t aa address valid to output valid 70 ns t avqx t oha address transition to output transition 10 ns t bhqz (2) t hzbe byte enable high to data hi-z 25 ns t blqv t dbe byte enable low to data valid 70 ns t blqx (2) t lzbe byte enable low to data transition 5 ns t e1hqz t e2lqz t hzce chip enable 1 high or chip enable 2 low to data hi-z 25 ns t e1lqv t e2hqv t ace chip enable 1 low or chip enable 2 high to data valid 70 ns t e1lqx t e2hqx t lzce chip enable 1 low or chip enable 2 high to data transition 10 ns t ghqz t hzoe output enable high to data hi-z 25 ns t glqv t doe output enable low to data valid 35 ns t glqx t lzoe output enable low to data transition 5 ns t pd (1) chip enable 1 high or chip enable 2 low to power down 70 ns t pu (1) chip enable 1 low or chip enable 2 high to power up 0 ns
m36w0r5020t0, M36W0R5020B0 18/26 figure 11. sram write ac waveforms, e1 s or e2 s controlled note: 1. w s , e1 s , e2 s and ub s ,lb s must be asserted to initiate a write cycle. 2. the i/o pins are in output mode and input signals should not be applied. 3. if e1 s , e2 s and w s are deasserted at the same time, dq0-dq15 remain high impedance. 4. ub s , lb s means both ub s and lb s . ai09883 tavav te1hax tdve1h tdve2l input valid a0-a17 e1 s w s dq0-dq15 valid e2 s tave1h tave2l tble1h tble2l tghdz te1hdx te2ldx tave1l ub s , lb s te2he2l te1le1h g s twle1h twle2l tave2h te2lax note 2
19/26 m36w0r5020t0, M36W0R5020B0 figure 12. sram write ac waveforms, w s controlled, g s high during write note: 1. w s , e1 s , e2 s and ub s ,lb s must be asserted to initiate a write cycle. 2. the i/o pins are in output mode and input signals should not be applied. 3. if e1 s , e2 s and w s are deasserted at the same time, dq0-dq15 remain high impedance. 4. ub s , lb s means both ub s and lb s . ai09884 tavav twhax tdvwh input valid a0-a17 e1 s w s dq0-dq15 valid e2 s tavwh tblwh tghdx twhdx tavwl ub s , lb s te2hwh te1lwh g s twlwh note 2
m36w0r5020t0, M36W0R5020B0 20/26 figure 13. sram write ac waveforms, w s controlled with g s low note: 1. during this period, the i/o pins are in ou tput mode and input signals should not be applied. 2. if e1 s , e2 s and w s are deasserted at the same time, dq0-dq15 remain high impedance. 3. ub s , lb s means both ub s and lb s . figure 14. sram write ac waveform, ub s and lb s controlled g s low note: 1. if e1 s , e2 s and w s are deasserted at the same time, dq0-dq15 remain high impedance. 2. the i/o pins are in output mode and input signals should not be applied. 3. ub s , lb s means both ub s and lb s . ai09885 tavav twhax tdvwh input valid a0-a17 e1 s w s dq0-dq15 valid e2 s tavwh twlwh tavwl twhdz twhdx tblwh ub s , lb s te1lwh te2hwh twldz note 1 ai09886 tavav tbhax tdvbh input valid a0-a17 e1 s w s dq0-dq15 valid e2 s tavbh twlbh tavbl tbhdx tblbh ub s , lb s te1lbh te2hbh note 2
21/26 m36w0r5020t0, M36W0R5020B0 table 10. sram write ac characteristics note: 1. whatever the temperature and voltage, t wldz is less than t whdx . symbol alt parameter m36w0r5020t0, M36W0R5020B0 unit min max t avav t wc write cycle time 70 ns t ave1l , t ave2h , t avwl t avbl t sa address valid to beginning of write 0 ns t avwh t ave1h t ave2l t avbh t aw address valid to write enable high 60 ns t blwh t ble1h t ble2l t blbh t bw ub s , lb s valid to end of write 60 ns t dve1h , t dve2l , t dvwh t dvbh t sd input valid to end of write 30 ns t e1hax , t e2lax , t whax t bhax t ha end of write to address change 0 ns t e1hdx , t e2ldx , t whdx t bhdx t hd data transition to end of write 0 ns t e1le1h , t e2he2l , t e1lwh t e2hwh t e1lbh , t e2hbh t sce chip enable 1 low or chip enable 2 high to end of write 60 ns t ghdz t hzoe output enable high to output hi-z 25 ns t whdz (1) t lzwe write enable high to input transition 10 ns t wldz (1) t hzwe write enable low to output hi-z 25 ns t wlwh t wle1h t wle2l t wlbh t pwe write enable pulse width 50 ns
m36w0r5020t0, M36W0R5020B0 22/26 figure 15. sram low v dds data retention ac waveforms, e1 s or ub s / lb s controlled figure 16. sram low v dds data retention ac waveforms, e2 s controlled table 11. sram low v dds data retention characteristic note: 1. sampled only. not 100% tested. symbol parameter test condition min max unit i dddr supply current (data retention) v dds = 1.0v, e1 s v dds ? 0.2v or e2 s 0.2v, v in v dds ? 0.2v or v in 0.2v 8a v dr supply voltage (data retention) 1.0 1.95 v t cdr chip disable to power down 0 ns t r operation recovery time 70 ns ai08197b e1 s or ub s , lb s tcdr v dds tr data retention mode v dds (min) v dds (min) v dr ai08198b e2 s tcdr v dds tr data retention mode v dds (min) v dds (min) v dr
23/26 m36w0r5020t0, M36W0R5020B0 package mechanical figure 17. stacked tfbga88 8x10mm - 8x10 active ball array, 0.8mm pitch, package outline note: drawing is not to scale. table 12. stacked tfbga88 8x10mm - 8x10 active ball array, 0.8mm pitch, mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.200 0.0079 a2 0.850 0.0335 b 0.350 0.300 0.400 0.0138 0.0118 0.0157 d 8.000 7.900 8.100 0.3150 0.3110 0.3189 d1 5.600 0.2205 ddd 0.100 0.0039 e 10.000 9.900 10.100 0.3937 0.3898 0.3976 e1 7.200 0.2835 e2 8.800 0.3465 e 0.800 ? ? 0.0315 ? ? fd 1.200 0.0472 fe 1.400 0.0551 fe1 0.600 0.0236 sd 0.400 0.0157 se 0.400 0.0157 a2 a1 a bga-z42 ddd d e e b se fd e2 d1 sd ball "a1" e1 fe fe1
m36w0r5020t0, M36W0R5020B0 24/26 part numbering table 13. ordering information scheme devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available op- tions (speed, package, etc.) or for further information on any aspect of this device, please contact the st- microelectronics sales office nearest to you. example: m36 w0 r 5 0 2 0 t 0 zaq t device type m36 = multi-chip package (flash + ram) flash 1 architecture w = multiple bank, burst mode flash 2 architecture 0 = none present operating voltage r = v ddf = v ddq =v ddp = 1.7 to 1.95v flash 1 density 5 = 32 mbit flash 2 density 0 = none present ram 1 density 2 = 4 mbit ram 0 density 0 = none present parameter blocks location t = top boot block flash b = bottom boot block flash product version 0 = 0.13m flash technology, 70ns; 0.15m ram, 70ns speed package zaq = stacked tfbga88 8 x 10mm - 8x10 active ball array, 0.8mm pitch option blank = standard packing t = tape & reel packing e = lead-free and rohs package, standard packing f = lead-free and rohs package, tape & reel packing
25/26 m36w0r5020t0, M36W0R5020B0 revision history table 14. document revision history date version revision details 27-aug-2003 1.0 first issue 06-may-2004 2.0 m36w0r5030t0 and m36w0r5030b0 part numbers and 8 mbit sram option removed. 0.15m flash memory technology replaced by the 0.13m technology. package specifications updated. e and f lead-free package options added to table 13., ordering information scheme . 17-dec-2004 3.0 document status promoted to full datasheet. flash memory and psram data updated. tfbga88 package fully compliant with the st ecopack specification.
m36w0r5020t0, M36W0R5020B0 26/26 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replac es all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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